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ad7466/ad7467/AD7468 rev. prf 11/02 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 analog devices, inc., 2002 1.6 v, micro-power, 8/10/12-bit adcs in 6 lead sot-23 preliminary technical data preliminary technical data functional block diagram features specified for v dd of 1.6 v to 3.6 v low power: 0.62 typ mw at 100 ksps with 3v supplies 0.48 typ mw at 50 ksps with 3.6 v supplies 0.12 typ mw at 100 ksps with 1.6v supplies fast throughput rate: 200ksps wide input bandwidth: 71db snr at 30 khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface spi/qspi/ wire/dsp compatible automatic power down standby mode: 0.5 a max 6-lead sot-23 package 8-lead msop package applications battery powered systems medical instruments remote data acquisition isolated data acquisition general description the ad7466/ad7467/AD7468 are 12-/10-/8-bit, high speed, low power, successive-approximation adcs respectively. the parts operate from a single 1.6v to 3.6v power supply and feature throughput rates up to 200ksps. the parts contain a low-noise, wide bandwidth track/hold amplifier which can handle input frequencies in excess of tbdkhz. the conversion process and data acquisition are controlled using and the serial clock, allowing the devices to interface with microprocessors or dsps. the input signal is sampled on the falling edge of and the conversion is also initiated at this point. there are no pipelined delays associated with the part. the ad7466/ad7467/AD7468 use advanced design tech- niques to achieve very low power dissipation at high throughput rates. the reference for the part is taken internally from v dd. this allows the widest dynamic input range to the adc. thus the analog input range for the part is 0 to v dd . the conversion rate is determined by the sclk. product highlights 1. specified for supply voltages of 1.6v to 3.6v. 2. 8-/10-/12-bit adcs in a sot-23 package. 3. high throughput rate with low power consumption. 4. flexible power/serial clock speed management. the conversion rate is determined by the serial clock allowing the conversion time to be reduced through the serial clock speed increase. automatic power down after conversion, which allows the average power consumption to be reduced when in power down. current consump- tion is 0.5 a max when in power down. 5. reference derived from the power supply. 6. no pipeline delay. the part features a standard successive-approximation adc with accurate control of the conversions via a input. t/h v in ad7466/67/68 v dd 12 /10 /8-bit successive approximation adc sclk control logic sdata cs gnd
?2? rev. prf preliminary technical data parameter b version 1, 2 unit test conditions/comments dynamic performance f in = 30 khz sine wave signal-to-noise + distortion (sinad) 2 70 db min signal-to-noise ratio (snr) 2 71 db min total harmonic distortion (thd) 2 ?78 db typ peak harmonic or spurious noise (sfdr) 2 ?80 db typ intermodulation distortion (imd) 2 fa = 29.1 khz, fb = 29.9 khz second order terms ?78 db typ third order terms ?78 db typ aperture delay 10 ns typ aperture jitter 30 ps typ full power bandwidth tbd mhz typ @ 3 db full power bandwidth tbd mhz typ @ 0.1 db dc accuracy resolution 12 bits integral nonlinearity 2 1.5 lsb max 0.6 lsb typ differential nonlinearity 2 ?0.9/+1.5 lsb max guaranteed no missed codes to 12 bits 0.75 lsb typ offset error 3 1.5 lsb max gain error 3 1.5 lsb max total unadjusted error (tue) 3 tbd lsb max analog input input voltage ranges 0 to v dd v dc leakage current 1 a max input capacitance 30 pf typ logic inputs input high voltage, v inh 0.7(v dd ) v min 1.6v vdd< 2.7v 2 v min 2.7v vdd 3.6v input low voltage, v inl 0.2(v dd ) v max 1.6v vdd< 1.8v 0.3(v dd ) v max 1.8v vdd< 2.7v 0.8 v max 2.7v vdd 3.6v input current, i in , sclk pin 1 a max typically 10 na, v in = 0 v or v dd input current, i in , pin 1 a typ input capacitance, c in 3 10 pf max logic outputs output high voltage, v oh v dd ? 0.2 v min i source = 200 a; v dd = 1.6 v to 3.6 v output low voltage, v ol 0.2 v max i sink = 200 a floating-state leakage current 10 a max floating-state output capacitance 3 10 pf max output coding straight (natural) binary conversion rate conversion time 4.70 s max 16 sclk cycles throughput rate 200 ksps max see serial interface section power requirements v dd 1.6/3.6 v min/max i dd digital i/ps = 0 v or v dd normal mode (static) tbd a typ v dd = 2.7v to 3.6v, sclk on or off tbd a typ v dd = 1.6v to 2.5v, sclk on or off normal mode (operational) 4 220 a max v dd = 3 v, f sample = 100 ksps 110 a typ v dd = 3 v, f sample = 50 ksps 20 a typ v dd = 3 v, f sample = 10 ksps 165 a max v dd = 2.5 v, f sample = 100 ksps 80 a typ v dd = 2.5 v, f sample = 50 ksps 16 a typ v dd = 2.5 v, f sample = 10 ksps 100 a max v dd = 1.8 v, f sample = 100 ksps 50 a typ v dd = 1.8 v, f sample = 50 ksps 10 a typ v dd = 1.8 v, f sample = 10 ksps (v dd = 1.6 v to 3.6 v, f sclk = 3.4 mhz, f sample = 100 ksps unless otherwise noted; t a = t min to t max , unless otherwise noted.) ad7466?specifications 1
?3? rev. prf preliminary technical data (v dd = 1.6 v to 3.6 v, f sclk = 3.4 mhz, f sample = 100 ksps unless otherwise noted; t a = t min to t max , unless otherwise noted.) ad7466?specifications 1 parameter b version 1, 2 unit test conditions/comments power requirements (continued) power-down 0.5 a max sclk off tbd a max sclk on power dissipation 5 normal mode (operational) 0.66 mw max v dd = 3v, f sample =100ksps 0.42 mw max v dd = 2.5v, f sample =100ksps 0.18 mw max v dd = 1.8v, f sample =100ksps power-down tbd w max v dd = 3v, sclk off tbd w max v dd = 2.5v, sclk off tbd w max v dd = 1.8v, sclk off notes 1 temperature ranges as follows: b versions: ?40c to +85c. 2 see terminology. 3 sample tested at 25c to ensure compliance. 4 see tpc10 supply current vs supply voltage. 5 see power consumption section. specifications subject to change without notice. ad7467?specifications 1 (v dd = 1.6 v to 3.6 v, f sclk = 3.4 mhz, f sample = 100 ksps unless otherwise noted; t a = t min to t max , unless otherwise noted.) parameter b version 1, 2 unit test conditions/comments dynamic performance f in = 30 khz sine wave, signal-to-noise + distortion (sinad) 2 61 db min total harmonic distortion (thd) 2 ?73 db max peak harmonic or spurious noise (sfdr) 2 ?74 db max intermodulation distortion (imd) 2 fa = 29.1 khz, fb = 29.9 khz second order terms ?78 db typ third order terms ?78 db typ aperture delay 10 ns typ aperture jitter 30 ps typ full power bandwidth tbd mhz typ @ 3 db full power bandwidth tbd mhz typ @ 0.1 db dc accuracy resolution 10 bits integral nonlinearity 1 lsb max differential nonlinearity 0.9 lsb max guaranteed no missed codes to 10 bits offset error 1 lsb max gain error 1 lsb max total unajusted error (tue) tbd lsb max analog input input voltage ranges 0 to v dd v dc leakage current 1 a max input capacitance 30 pf typ logic inputs input high voltage, v inh 0.7(v dd ) v min 1.6v vdd< 2.7v 2 v min 2.7v vdd 3.6v input low voltage, v inl 0.2(v dd ) v max 1.6v vdd< 1.8v 0.3(v dd ) v max 1.8v vdd< 2.7v 0.8 v max 2.7v vdd 3.6v input current, i in , sclk pin 1 a max typically 10 na, v in = 0 v or v dd input current, i in , pin 1 a typ input capacitance, c in 3 10 pf max
?4? rev. prf preliminary technical data ad7467?specifications 1 (v dd = 1.6 v to 3.6 v, f sclk = 3.4 mhz, f sample = 100 ksps unless otherwise noted; t a = t min to t max , unless otherwise noted.) notes 1 temperature ranges as follows: b versions: ?40c to +85c. 2 see terminology. 3 sample tested at 25c to ensure compliance. 4 see power consumption section. specifications subject to change without notice. AD7468?specifications 1 (v dd = 1.6 v to 3.6 v, f sclk = 3.4 mhz, f sample = 100 ksps unless otherwise noted; t a = t min to t max , unless otherwise noted.) parameter b version 1, 2 unit test conditions/comments dynamic performance f in =30 khz sine wave signal-to-noise + distortion (sinad) 2 49 db min total harmonic distortion (thd) 2 ?65 db max peak harmonic or spurious noise (sfdr) 2 ?65 db max intermodulation distortion (imd) 2 fa = 29.1 khz, fb = 29.9 khz second order terms ?68 db typ third order terms ?68 db typ aperture delay 10 ns typ aperture jitter 30 ps typ full power bandwidth tbd mhz typ @ 3 db full power bandwidth tbd mhz typ @ 0.1 db dc accuracy resolution 8 bits integral nonlinearity 0.5 lsb max differential nonlinearity 0.5 lsb max guaranteed no missed codes to 8 bits offset error 0.5 lsb max gain error 0.5 lsb max total unadjusted error (tue) 0.5 lsb max parameter b version 1, 2 unit test conditions/comments logic outputs output high voltage, v oh v dd ? 0.2 v min i source = 200 a; output low voltage, v ol 0.2 v max i sink = 200 a floating-state leakage current 10 a max floating-state output capacitance 3 10 pf max output coding straight (natural) binary conversion rate conversion time 3.52 s max 12 sclk cycles with sclk at 3.4 mhz throughput rate 275 ksps max see serial interface section power requirements v dd 1.6/3.6 v min/max i dd digital i/ps = 0 v or v dd normal mode (static) tbd a typ v dd = 2.7v to 3.6v, sclk on or off tbd a typ v dd = 1.6v to 2.5v, sclk on or off normal mode (operational) 200 a max v dd = 3v, f sample =100 ksps 150 a max v dd = 2.5v, f sample =100 ksps 90 a max v dd = 1.8v, f sample =100 ksps power-down 0.5 a max sclk off tbd a max sclk on power dissipation 4 normal mode (operational) 0.6 mw max v dd = 3v, f sample =100ksps 0.38 mw max v dd = 2.5v, f sample =100ksps 0.17 mw max v dd = 1.8v, f sample =100ksps power-down tbd w max v dd = 3v, sclk off tbd w max v dd = 2.5v, sclk off tbd w max v dd = 1.8v, sclk off
?5? rev. prf preliminary technical data notes 1 temperature ranges as follows: b versions: ?40c to +85c. 2 see terminology. 3 sample tested at 25c to ensure compliance. 4 see power consumption section. specifications subject to change without notice. analog input input voltage ranges 0 to v dd v dc leakage current 1 a max input capacitance 30 pf typ logic inputs input high voltage, v inh 0.7(v dd ) v min 1.6v vdd< 2.7v 2 v min 2.7v vdd 3.6v input low voltage, v inl 0.2(v dd ) v max 1.6v vdd< 1.8v 0.3(v dd ) v max 1.8v vdd< 2.7v 0.8 v max 2.7v vdd 3.6v input current, i in , sclk pin 1 a max typically 10 na, v in = 0 v or v dd input current, i in , pin 1 a typ input capacitance, c in 3 10 pf max logic outputs output high voltage, v oh v dd ? 0.2 v min i source = 200 a; v dd = 1.6 v to 3.6 v output low voltage, v ol 0.2 v max i sink = 200 a floating-state leakage current 10 a max floating-state output capacitance 3 10 pf max output coding straight (natural) binary conversion rate conversion time 2.94 s max 10 sclk cycles with sclk at 3.4 mhz throughput rate 320 ksps max see serial interface section power requirements v dd 1.6/3.6 v min/max i dd digital i/ps = 0 v or v dd normal mode (static) tbd a typ v dd = 2.7v to 3.6v, sclk on or off tbd a typ v dd = 1.6v to 2.5v, sclk on or off normal mode (operational) 175 a max v dd = 3 v, f sample = 100 ksps 135 a max v dd = 2.5 v, f sample = 100 ksps 80 a max v dd = 1.8 v, f sample = 100 ksps power-down 0.5 a max sclk off tbd a max sclk on power dissipation 4 normal mode (operational) 0.54 mw max v dd = 3v, f sample =100ksps 0.34 mw max v dd = 2.5v, f sample =100ksps 0.15 mw max v dd = 1.8v, f sample =100ksps power-down tbd w max v dd = 3v, sclk off tbd w max v dd = 2.5v, sclk off tbd w max v dd = 1.8v, sclk off parameter b version 1, 2 unit test conditions/comments AD7468?specifications 1 (v dd = 1.6 v to 3.6 v, f sclk = 3.4 mhz, f sample = 100 ksps unless otherwise noted; t a = t min to t max , unless otherwise noted.)
?6? rev. prf preliminary technical data ad7466/ad7467/AD7468 limit at t min , t max parameter ad7466/ad7467/AD7468 units description f sclk 2 10 khz min 3 3.4 mhz max t convert 16 x t sclk ad7466 12 x t sclk ad7467 10 x t sclk AD7468 t quiet t b d ns min minimum quiet time required between bus relinquish and start of next conversion t 1 tbd ns min minimum pulsewidth t 2 10 ns min to sclk setup time t 3 4 tbd ns max delay from until sdata 3-state disabled t 4 4 t b d ns max data access time after sclk falling edge t 5 0.4t sclk ns min sclk low pulse width t 6 0.4t sclk ns min sclk high pulse width t 7 t b d ns min sclk to data valid hold time t 8 5 tbd ns max sclk falling edge to sdata high impedance t power-up tbd s max power up time from power down. notes 1 sample tested at +25c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of tbd volts. 2 mark/space ratio for the sclk input is 40/60 to 60/40. 3 minimum f sclk at which specifications are guaranteed. 4 measured with the load circuit of figure 1 and defined as the time required for the output to cross the vih or vil voltage. 5 t 8 is derived form the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 8 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. specifications subject to change without notice. figure 1. load circuit for digital output timing specifications +1.6v i ol 200a 200a i oh to output pin c l 50pf timing specifications 1 ( v dd = +1.6 v to +3.6 v; t a = t min to t max , unless otherwise noted.)
? 7 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 timing example 1 from figure 3, having f sclk = 3.4mhz and a throughput of 100 ksps, gives a cycle time of t convert + t 8 + t quiet = 10 s. with t convert = t 2 + 15(1/f sclk ) = 10 ns + 4.41 s = 4.42 s, and t 8 = tbd ns min, this leaves t quiet to be tbd ns. this tbd ns satisfies the requirement of tbd ns for t quiet . the part is fully powered up and the signal is fully acquired at point a, that means the acquisition/power up time is t 2 + 2(1/f sclk ) = 10 ns + 0.588 s = 0.59 s satisfying the maximum requirement of tbd s for the power up time. timing example 2 the ad7466 can also operate with slower clock frequencies. from figure 3, having f sclk = 2mhz and a throughput of 50 ksps, gives a cycle time of t convert + t 8 + t quiet = 20 s. with t convert = t 2 + 15(1/f sclk ) = 10 ns + 7.5 s = 7.51 s, and t 8 = tbd ns min, this leaves t quiet to be tbd ns. this tbd ns satisfies the requirement of tbd ns for t quiet . the part is fully powered up and the signal is fully acquired at point a, that means the acquisition/power up time is t 2 + 2(1/f sclk ) = 10 ns + 1 s = 1.01 s, satisfying the maximum requirement of tbd s for the power up time. as in this example and with other slower clock values, the part will be fully powered up and the signal already be acquired before the third sclk falling edge, however the track and hold will not go into hold mode until that point. in this example, the part may be powered up and the signal may be fully acquired at approximately point b in figure 3. figure 2. ad7466 serial interfacetiming diagram figures 2 and 3 show some of the timing parameters from the timing specifications section. &6 sclk 1 5 13 15 sdata 4 leading zero?s 3-state t 4 2 34 16 t 5 t 3 t quiet t convert t 2 3- state db11 db10 db2 db0 t 6 t 7 t 8 14 zero ze r o ze r o z a db1 figure 3. serial interfacetiming example sclk 1 5 2 34 &6 13 15 16 t quiet t 2 t 8 14 a 1/throughput t convert track/hold in track automatic power down track/hold in hold pointa:thepartisfullypoweredupwithv in fully acquired b
? 8 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 absolute maximum ratings 1 (t a = +25c unless otherwise noted) v dd to gnd......................................?0.3 v to tbd v analog input voltage to gnd......?0.3 v to v dd + 0.3 v digital input voltage to gnd....................?0.3 v to 7 v digital output voltage to gnd....?0.3 v to v dd + 0.3 v input current to any pin except supplies 2 .........10 ma operating temperature range commercial (a, b version)................?40c to +85c storage temperature range..............?65c to +150c junction temperature........................................+150c sot-23 package ja thermal impedance ...............................229.6 c/w jc thermal impedance ............................... 91.99c/w msop package ja thermal impedance ............................... 205.9c/w jc thermal impedance ............................... 43.74c/w caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7466/ad7467/AD7468 feature proprietary esd protection circuitry, per- manent damage may occur on devices subjected to high energy electrostatic discharges. there- fore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide temperature linearity package branding model range error (lsb) 1 option 2 information ad7466brt ?40c to +85c 1.5 max rt-6 clb ad7466brm ?40c to +85c 1.5 max rm-8 clb ad7467brt ?40c to +85c 1 max rt-6 cmb ad7467brm ?40c to +85c 1 max rm-8 cmb AD7468brt ?40c to +85c 0.5 max rt-6 cnb AD7468brm ?40c to +85c 0.5 max rm-8 cnb eval-ad7466cb 3 eval-ad7467cb 3 eval-control brd2 4 notes 1 linearity error here refers to integral nonlinearity. 2 rt = sot-23, rm = msop. 3 this can be used as a stand-alone evaluation board or in conjunction with the eval-control board for evaluation/demostration purposes. 4 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. to order a complete evaluation kit you will need to order the particular adc evaluation board, e.g. eval-ad7466cb, the eval-control brd2 and a 12v ac transformer. see relevant evaluation board technical note for more information. lead temperature, soldering vapor phase (60 secs)....................................+215c infared (15 secs)............................................+220c esd..............................................................tbd kv notes 1 stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch up.
? 9 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 pin function description pin mnemonic function chip select. active low logic input. this input provides the dual function of initiating conversions on the ad7466/ad7467/AD7468 and also frames the serial data transfer. v dd power supply input. the v dd range for the ad7466/ad7467/AD7468 is from +1.6v to +3.6v. g n d analog ground. ground reference point for all circuitry on the ad7466/ad7467/AD7468. all analog input signals should be referred to this gnd voltage. v in analog input. single-ended analog input channel. the input range is 0 to v dd . sdata d ata out. logic output. the conversion result from the ad7466/ad7467/AD7468 is pro- vided on this output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream from the ad7466 consists of four leading zeros followed by the 12 bits of conversion data which is provided msb first. the data stream from the ad7467 consists of four leading zeros followed by the 10 bits of conversion data, which is provided msb first. the data stream from the AD7468 consists of four leading zeros followed by the 8 bits of conversion data, which is provided msb first. sclk serial clock. logic input. sclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source for the ad7466/ad7467/AD7468's conver- sion process. n c no connect. ad7466/67/68 pin configuration ad7466/67/68 top view 1 2 3 45 6 7 8 nc &6 sdata sclk v dd gnd v in (not to scale) nc 6-lead sot-23 8-lead msop 1 2 3 4 5 6 &6 sdata sclk v dd gnd v in ad7466/67/68 top view (not to scale)
? 10 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 terminology integral nonlinearity this is the maximum deviation from a straight line pass- ing through the endpoints of the adc transfer function. for the ad7466/67/68 the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e agnd + 1 lsb. gain error this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., v ref ? 1lsb) after the offset error has been adjusted out. track/hold acquisition time the track/hold acquisition time is the time required for the part to acquire a worse case input value within 0.5 lsb. for the ad7466/67/68 the part enters track mode on the falling edge and it returns to hold mode on the third sclk falling edge. the part remains in hold mode until the following falling edge. see figure 3 and the serial interface section for more details. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distor- tion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db and for a 10- bit converter this is 62db. total unadjusted error this is a comprehensive specification which includes gain error, linearity error and offset error. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7466/ ad7467/AD7468, it is defined as: where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms in- clude (fa + fb) and (fa ? fb), while the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) and (fa ? 2fb). the ad7466/ad7467/AD7468 are tested using the ccif standard where two input frequencies are used. in this case, the second order terms are usually distanced in fre- quency from the original sine waves while the third order terms are usually at a frequency close to the input frequen- cies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual dis- tortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. thd (db ) 20 log v 2 2 v 3 2 v 4 2 v 5 2 v 6 2 v 1
? 11 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 performance curves dynamic performance curves tpc 1, tpc 2 and tpc 3 show a typical fft plot for the ad7466, ad7467 and AD7468 respectively, at 100ksps sample rate and 30 khz input frequency. tpc 4 shows the signal-to-(noise+distortion) ratio performance versus input frequency for various supply voltages while sampling at 100ksps with a sclk frequency of 3.4mhz for the ad7466. tpc 5 shows the signal to noise ratio (snr) performance versus input frequency for various supply voltages while sampling at 100ksps with a sclk frequency of 3.4mhz for the ad7466. tpc 6 shows a graph of the total harmonic distortion versus analog input signal frequency for various supply voltages while sampling at 100ksps with a sclk frequency of 3.4mhz for the ad7466. tpc 7 shows a graph of the total harmonic distortion versus analog input frequency for different source impedances when using a supply voltage of 2.7v, sclk frequency of 3.4mhz and sampling at a rate of 100ksps for the ad7466. see analog input section. title 0 0 t i t l e tbd title 0 0 t i t l e tbd tpc 1. ad7466 dynamic performance at 100ksps tpc 2. ad7467 dynamic performance at 100ksps dc accuracy curves tpc 8 and tpc 9 show typical inl and dnl performance for the ad7466. power requirements curves tpc10 shows the supply current versus supply voltage for the ad7466 at -40 o c, 25 o c and 85 o c, with sclk frequency of 3.4mhz and a sampling rate of 100ksps. tpc11 shows the peak current versus supply voltage for the ad7466 with sclk frequency of 3.4mhz. tpc12 shows the shutdown current versus supply voltage tpc13 shows the power consumption vs throughput rate for the ad7466 with a sclk of 3.4mhz and different supply voltages. see power consumption section for more details. typical performance characteristics
? 12 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 title 0 0 t i t l e tbd tpc 8. ad7466 inl performance tpc 7. thd vs. analog input frequency for various source impedance tpc 5. ad7466 snr vs analog input frequency at 100ksps for various supply voltages tpc 3. AD7468 dynamic performance at 100ksps tpc 4. ad7466 sinad vs analog input frequency at 100ksps for various supply voltages title 0 0 t i t l e tbd tpc 6. thd vs. analog input frequency at 100ksps for various supply voltages -73 -72 -71 -70 -69 -68 -67 -66 -65 10 100 1000 input frequency - khz sinad - db tem p = 25 o c v dd = 3 . 6 v v dd = 1 . 6 v v dd = 1 . 8 v v dd = 2 . 2 v v dd = 2 . 7 v v dd = 3 v -85 -83 -81 -79 -77 -75 -73 -71 -69 -67 -65 10 100 1000 input frequency - kh z thd - db tem p = 25 o c v dd = 3 . 6 v v dd = 1 . 6 v v dd = 1 . 8 v v dd = 2 . 2 v v dd = 2 . 7 v v dd = 3 v -84 -83 -82 -81 -80 -79 -78 -77 -76 10 100 1000 i nput frequency - khz thd - db temp = 25 o c v dd = 2 . 7 v r in = 1 k : r in = 10 : r in = 100 : r in = 510 : r in = 0 : -73 -72.5 -72 -71.5 -71 -70.5 -70 -69.5 -69 -68.5 -68 10 100 1000 input frequency - khz snr - db temp = 25 o c v dd = 3 . 6 v v dd = 1 . 6 v v dd = 1 . 8 v v dd = 2 . 2 v v dd = 2 . 7 v v dd = 3 v
? 13 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 tpc 9. ad7466 dnl performance title 0 0 t i t l e tbd title 0 0 t i t l e tbd tpc 10. supply current vs supply voltage, sclk 3.4mhz tpc 11. peak current vs supply voltage, sclk 3.4mhz tpc 12. shutdown current vs supply voltage tpc 13. power consumption vs throughput rate, sclk 3.4mhz 65 90 115 140 165 190 215 240 265 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 supply voltage - volts supply current - a temp = -40 o c temp = 85 o c temp = 25 o c f sample = 100 ksps 135 185 235 285 335 385 435 485 535 585 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 supply voltage - volts peak current - a temp = 25 o c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 50 100 150 200 250 throughput - ksps power - mw v dd = 3.0 v v dd = 1.8 v v dd = 2.2 v temp = 25 o c v dd = 2.7 v
? 14 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 circuit information the ad7466/ad7467/AD7468 are fast, micro-power, 12-/ 10-/8-bit, a/d converters respectively. the parts can be operated from a +1.6 v to +3.6 v supply. when operated from any supply voltage within this range, the ad7466/ ad7467/AD7468 is capable of throughput rates of 200ksps when provided with a 3.4 mhz clock. the ad7466/ad7467/AD7468 provides the user with an on-chip track/hold, a/d converter, and a serial interface housed in a tiny 6-lead sot-23 or 8-lead msop package, which offer the user considerable space saving advantages over alternative solutions. the serial clock input accesses data from the part but also provides the clock source for the successive-approximation a/d converter. the analog input range is 0 to v dd . an external reference is not required for the adc and neither is there a reference on- chip. the reference for the ad7466/ad7467/AD7468 is derived from the power supply and thus giving the widest dynamic input range. the ad7466/ad7467/AD7468 also features an automatic power-down mode option to allow power saving between conversions. the power-down feature is implemented across the standard serial interface as described in the mode of operation section. adc transfer function the output coding of the ad7466/ad7467/AD7468 is straight binary. the designed code transitions occur at successive integer lsb values (i.e., 1lsb, 2lsbs, etc.). the lsb size is v dd /4096 for the ad7466, v dd /1024 for the ad7467, and v dd /256 for the AD7468 . the ideal transfer characteristic for the ad7466/ad7467/ AD7468 is shown in figure 6. converter operation the ad7466/ad7467/AD7468 is a successive approxi- mation analog-to-digital converter based around a charge redistribution dac. figures 4 and 5 show simplified schematics of the adc. figure 4 shows the adc during its acquisition phase. sw2 is closed and sw1 is in posi- tion a, the comparator is held in a balanced condition and the sampling capacitor acquires the signal on v in . when the adc starts a conversion, see figure 5, sw2 will open and sw1 will move to position b causing the comparator to become unbalanced. the control logic and the charge redistribution dac are used to add and sub- tract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced the conversion is com- plete. the control logic generates the adc output code. figure 6 shows the adc transfer function. figure 4. adc acquisition phase figure 5. adc conversion phase figure 6. ad7466/ad7467/AD7468 transfer characteristic charge redistribution dac v in v dd /2 sampling capacitor comparator control logic acqui sition phase sw1 a b sw2 agnd charge redistribution dac v in v dd /2 sampling capacitor comparator control logic conversion phase sw1 a b sw2 agnd 000...000 0v a d c c o d e analog input 111...111 000...001 000...010 111...110 111...000 011...111 1lsb +v dd -1lsb 1lsb = v dd /4096 (ad7466) 1lsb = v dd /1024 (ad7467) 1lsb = v dd /256 (AD7468)
? 15 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 figure 7. ref191 as power supply to ad7466/ad7467/AD7468 analog input figure 8 shows an equivalent circuit of the analog input structure of the ad7466/ad7467/7468. the two diodes d1 and d2 provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300mv. this will cause these diodes to become forward biased and start conducting current into the substrate. the capacitor c1 in figure 8 is typically about 4pf and can primarily be at- tributed to pin capacitance. the resistor r1 is a lumped component made up of the on resistance of a switch. this resistor is typically about 200 . the capacitor c2 is the adc sampling capacitor and has a capacitance of 16pf typically. v dd v in gnd +5v supply 0.1f 10f ref191 0.1f 1f tant +2.048v ad7466/67/68 0v tov dd input sdata c /p sclk serial interface &6 tbd a 680nf typical connection diagram figure 7 shows a typical connection diagram for the ad7466/ad7467/AD7468. v ref is taken internally from v dd and therefore v dd should be well decoupled. this provides an analog input range of 0v to v dd . the conversion result consists of four leading zeros followed by the msb of the 12-bit, 10-bit or 8-bit result from the ad7466, ad7467 or AD7468 respectively. see serial interface section. alternatively, because the supply current required by the ad7466/ad7467/AD7468 is so low, a precision reference can be used as the supply source to the ad7466/ad7467/ AD7468. the ref19x series are precision micropower, low dropout voltage references. for the ad7466/67/68 voltage range operation, the ref193 for 3v, ref192 for 2.5 v and ref191 for 2.048v can be used to supply the required voltage to the adc - see figure 7. this configu- ration is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 3v or 2.5v (e.g. 5v). the ref19x will output a steady voltage to the ad7466/ad7467/AD7468. if the low dropout ref191 is used, the current it needs to supply to the ad7466/ad7467/AD7468 is typically tbd a . when the adc is converting at a rate of 100ksps the ref191 will need to supply a maximum of 150 a to the ad7466/ad7467/AD7468. the load regulation of the ref191 is typically 10 ppm/ma (ref191, v s = 5v), which results in an error of 1.5 ppm (3.07 v) for the 150 a drawn from it. this corresponds to a 0.0061 lsb error for the ad7466 with v dd = 2.048v from the ref191, a 0.0015 lsb error for the ad7467, and a 0.00038 lsb error for the AD7468. for applica- tions where power consumption is important, the automatic power down mode of the adc and the sleep mode of the ref19x reference should be used to improve power performance. see mode of operation section of the datasheet. reference tied ad7466 snr performance to v dd 10khz input ref191@2.048v tbd db adr420 tbd db ref192@2.5 tbd db ad780 tbd db ref43 tbd db adr421 tbd db ref193@3v tbd db ad780 tbd db adr423 tbd db table i. ad7466 performance for various voltage references ic. table i provides some typical performance data with vari- ous references used as a v dd source with a low frequency analog input under the same set-up conditions. v in d1 v dd d2 r1 c2 16pf c1 4pf conversion phase - switch open track phase - switch closed figure 8. equivalent analog input circuit
? 16 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 digital inputs the digital inputs applied to the ad7466/ad7467/ AD7468 are not limited by the maximum ratings which limit the analog inputs. instead, the digitals inputs applied can go to 7v and are not restricted by the v dd + 0.3v limit as on the analog input. for example, if the ad7466/ ad7467/AD7468 were operated with a v dd of 3v then 5v logic levels could be used on the digital inputs. however, it is important to note that the data output on sdata will still have 3v logic levels when v dd = 3v. another advantage of sclk and not being restricted by the v dd + 0.3v limit is the fact that power supply sequencing issues are avoided. if or sclk are applied before v dd then there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3v was applied prior to v dd . mode of operation the ad7466/ad7467/AD7468 automatically enters power down at the end of each conversion. this mode of operation is designed to provide flexible power manage- ment options and to optimize the power dissipation/ throughput rate ratio for low power applications require- ments. figure 9 shows the general diagram of the operation for the ad7466/ad7467/AD7468. on the falling edge the part begins to power up and the track and hold, which was in hold while the part was in power down, will go into track mode. the conversion is also initiated at this point. when operating the part with a 3.4 mhz clock it will take 2 clock cycles to fully power up the part and acquire the input signal. on the third sclk falling edge after the falling edge the track and hold will return to hold mode. for the ad7466 sixteen serial clock cycles are required to complete the conversion and access the complete conver- sion result. the ad7466 will automatically enter power down mode on the 16th sclk falling edge. for the ad7467 fourteen serial clock cycles are required to complete the conversion and access the complete con- version result. the ad7467 will automatically enter power down mode on the 14th sclk falling edge. figure 9. normal mode operation for ac applications, removing high frequency components from the analog input signal is recommended by use of a band-pass filter on the relevant analog input pin. in appli- cations where harmonic distortion and signal to noise ratio are critical the analog input should be driven from a low impedance source. large source impedances will significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the op amp will be a function of the particular application. table ii provides some typical performance data with various op amps used as the input buffer with a low frequency analog input under the same set-up conditions. the ad8631 low power op-amp is ideal for battery- powered applications. it works from single supply voltages as low as 1.8v, it has low supply current and the small package, 5-lead sot-23, offers considerable space saving advantages. when no amplifier is used to drive the analog input the source impedance should be limited to low values. the maximum source impedance will depend on the amount of total harmonic distortion (thd) that can be tolerated. the thd will increase as the source impedance increases and performance will degrade. tpc7 shows a graph of the total harmonic distortion vs. analog input signal frequency for different source impedances when using a supply voltage of tbdv and sampling at a rate of 100 ksps. op amp in the ad7466 snr performance input buffer 10khz input ad711 tbd db ad820 tbd db ad8631 tbd db table ii. ad7466 performance for various input buffers. valid data 16 1 the part begins to power up 3 2 14 12 sclk sdata AD7468 enters power down &6 canbeheldlow ad7467 enters power down &6 canbeheldlow ad7466 enters power down &6 canbeheldlow
? 17 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 power consumption the ad7466/67/68 automatically enters power down mode at the end of each conversion or if is brought high before the conversion is finished. when the ad7466/67/68 is in power down mode all the analog circuitry is powered down and the current consumption is typically tbd a. to achieve the lowest power dissipation, there are some considerations the user should bear in mind. the conversion time is determined by the serial clock frequency. the faster the sclk frequency, the shorter the conversion time. this implies as the frequency increases the part will be dissipating power for a shorter period of time, when the conversion is taking place, and it will remain in power down mode for a longer period of time. figure 10 shows two ad7466 running with two different sclk frequencies, sclk a and sclk b, sclk a having the higher sclk frequency. for the same throughput rate, the ad7466 using sclk a will have a shorter conversion time than the ad7466 using sclk b and it will remain in power down mode for longer. the current consumption in power down mode is very low, and the average power consumption will be greatly reduced. this can be seen in figure 11. this figure shows the supply current versus sclk frequency for various supply voltages at a throughput rate of 100ksps. for a fixed throughput rate, the supply current (average current) will drop as the sclk frequency increases, due to the fact that the part will be in power down mode most of the time. it can also be seen, that for a lower supply voltage the supply current drops accordingly. figure 10. conversion time comparison for different sclk frequencies for a fixed throughput rate sclk a 1 16 1 16 &6 sclk b conversion time a conversion time b 1/throughput for the AD7468 twelve serial clock cycles are required to complete the conversion and access the complete conver- sion result. the AD7468 will automatically enter power down mode on the 12th sclk falling edge. the ad7466 will also enter power down mode, if is brought high any time before the 16th sclk falling edge. the conversion that was initiated by the falling edge will be terminated and sdata will go back into three- state. this also applies for the ad7467 and AD7468, if is brought high before the conversion is complete (the 14th sclk falling edge for the ad7467, and the 12th sclk falling edge for the AD7468) the part will enter power down, the conversion will be terminated and sdata will go back into three-state. when supplies are first applied to the ad7466/ad7467/ AD7468 a dummy conversion should be performed to ensure that the part is in power down mode. may idle high until the next conversion or may idle low until returns high sometime prior to the next conversion, (effectively idling low). once a data transfer is complete (sdata has returned to three-state), another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing low again. figure 11. supply current vs sclk frequency for a fixed throughput rate and different supply voltages 60 90 120 150 180 210 240 270 300 330 360 390 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 sclk frequency - mhz supply current - a v dd = 1.6v v dd = 3.6v v dd = 2.7v v dd = 2.2v v dd = 1.8v f sample = 100 ksps temp = 25 o c v dd = 3.0v
? 18 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 figure 13. power vs throughput for different sclk and supply voltages figure 12. conversion time vs power down time for a fixed sclk frequency and different throughput rates 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 50 100 150 200 250 throughput - ksps power - mw v dd = 1.8 v, sclk = 3.4 mhz v dd = 3.0 v, sclk = 2 .4 mhz v dd = 3.0 v, sclk = 3.4 mhz v dd = 1.8 v, sclk = 2.4 mhz temp = 25 o c sclk 1 16 &6 a &6 b conversion time a power down time a power down time b 1/throughput a 1/throughput b conversion time b the following two examples will illustrate by means of some calculations, what has been explained in this section. power consumption example 1 this example shows that for a fixed throughput rate, as the sclk frequency increases the average power consumption drops. from figure 10, having sclk a= 3.4 mhz, sclk b= 1.2 mhz and a throughput rate of 50ksps, which gives a cycle time of 20 s, the following values can be obtained: conversion time a = 16 x (1/sclk a) = 4.7 s (23.5% of the cycle time) power down time a = (1/throughput) - conversion time a = 20 s - 4.7 s = 15.3 s (76.5% of the cycle time) conversion time b = 16 x (1/sclk b) = 13 s (65% of the cycle time) power down time b = (1/throughput) - conversion time b = 20 s - 13 s = 7 s (35% of the cycle time) tpc14 in the performance curves section, shows power consumption versus throughput rate for a 3.4mhz sclk frequency. in this case the conversion time will be the same for all the cases, as the sclk frequency is a fixed parameter. low throughput rates will lead to lower current consumptions, with a higher percentage of the time in power down mode. figure 12 shows two ad7466 running with the same sclk frequency but at different throughput rates. the throughput rate for the ad7466 called a is higher than for the ad7466 called b. the slower the throughput rate, the longer the period of time the part will be in power down mode, and the average power consumption will drop accordingly. figure 13 shows power versus throughput rate for different supply voltages and sclk frequencies. in this plot all the elements that have been explained above, that is, the influence of the sclk frequency, the influence of the throughput rate and the influence of the supply voltage, in the power consumption are taken into consideration.
? 19 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 the average power consumption includes the power dissipated when the part is converting and the power dissipated when the part is in power down mode. the average power dissipated during conversion is calculated as the percentage of the cycle time spent when converting multiplied by the peak current during conversion. the average power dissipated when in power down mode is calculated as the percentage of the cycle time spent in power down mode multiplied by the current figure for power down mode. in order to obtain the value for the average power, these terms must be multiplied by the voltage. considering the peak current for each sclk frequency for v dd = 1.8v, power consumption a = ((4.7/20) x 186 a + (15.3/20) x 1 a) x 1.8v = (43.71+0.765) a x1.8v = 80 w = 0.08 mw power consumption b = ((13/20) x 108 a + (7/20) x 1 a) x 1.8v = (70.2+0.35) a x1.8v = 126.99 w = 0.127 mw it can be concluded that for a fixed throughput rate, the average power consumption drops as the sclk frequency increases. power consumption example 2 er coxample 2 this example shows that for a fixed sclk frequency, as the throughput rate decreases the average power consumption drops. from figure 12, for sclk = 3.4 mhz, throughput a = 100ksps (which gives a cycle time of 10 s) and throughput b = 50ksps (which gives a cycle time of 20 s) the following values can be obtained: conversion time a = 16 x (1/sclk) = 4.7 s (47% of the cycle time for a throughput of 100ksps) power down time a = (1/throughput a) - conversion time a = 10 s - 4.7 s = 5.3 s (53% of the cycle time) conversion time b = 16 x (1/sclk) = 4.7 s (23.5% of the cycle time for a throughput of 50ksps) power down time b = (1/throughput b) - conversion time b = 20 s - 4.7 s = 15.3 s (76.5% of the cycle time) the average power consumption is calculated as it has been explained in the power consumption example1, considering the peak current for a 3.4mhz sclk frequency for v dd = 1.8v. power consumption a = ((4.7/10) x 186 a + (5.3/10) x 1 a)x 1.8v= (87.42+0.53) a x1.8v= 158.3 w= 0.156 mw power consumption b = ((4.7/20) x 186 a + (15.3/20) x 1 a) x 1.8v= (43.7+0.765) a x1.8v = 80 w = 0.08 mw it can be concluded that for a fixed sclk frequency, the average power consumption drops as the throughput rate decreases. serial interface figures 14, 15, 16 show the detailed timing diagram for serial interfacing to the ad7466/ad7467/AD7468.the serial clock provides the conversion clock and also con- trols the transfer of information from the adc during a conversion. on the falling edge the part begins to power up. the falling edge of puts the track and hold into track mode and takes the bus out of three-state. the conversion is also initiated at this point. on the third sclk falling edge after the falling edge, the part should be fully powered up, as shown in figure 14 at point b, and the track and hold will return to hold. for the ad7466, on the 16th sclk falling edge the sdata line will go back into three-state and the part will enter power down. if the rising edge of occurs before 16 sclks have elapsed then the conversion will be terminated, the sdata line will go back into three-state and the part will enter power down, otherwise sdata returns to three-state on the 16th sclk falling edge as shown in figure 14. sixteen serial clock cycles are re- quired to perform the conversion process and to access data from the ad7466. figure 14. ad7466 serial interface timing diagram &6 sclk 1 5 13 15 4 leading zero ? s 3-state t 4 2 34 16 t 5 t 3 t quiet t convert t 2 3-state db 1 1 db 1 0 db2 db0 t 6 t 7 t 8 14 zero zero zero z b db1 sdata
? 20 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 for the ad7467, the 14th sclk falling edge will cause the sdata line to go back into three-state and the part will enter power down. if the rising edge of occurs before 14 sclks have elapsed then the conversion will be terminated, the sdata line will go back into three-state and the ad7467 will enter power down, otherwise sdata returns to three-state on the 14th sclk falling edge as shown in figure 15. fourteen serial clock cycles are required to perform the conversion process and to access data from the ad7467. for the AD7468, the 12th sclk falling edge will cause the sdata line to go back into three-state and the part will enter power down. if the rising edge of occurs before 12 sclks have elapsed then the conversion will be terminated, the sdata line will go back into three-state and the AD7468 will enter power down, otherwise sdata returns to three-state on the 12th sclk falling edge as shown in figure 16. twelve serial clock cycles are required to perform the conversion process and to access data from the AD7468. going low provides the first leading zero to be read in by the microcontroller or dsp. the remaining data is figure 15. ad7467 serial interface timing diagram &6 sclk 1 5 13 sdata 4 leading zero ? s 3-state t 4 2 34 t 3 t quiet t convert t 2 3-state db9 db8 db0 t 6 t 7 t 8 14 zero zero ze r o z b t 5 then clocked out by subsequent sclk falling edges be- ginning with the 2nd leading zero, thus the first clock falling edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. for the ad7466 the final bit in the data transfer is valid on the 16th sclk falling edge, having being clocked out on the previous (15th) sclk falling edge. in applications with a slow sclk, it is possible to read in data on each sclk rising edge. in that case, the first falling edge of sclk will clock out the second leading zero and it could be read in the first rising edge. however, the first leading zero that was clocked out when went low will be missed unless it was not read in the first falling edge. the 15th falling edge of sclk will clock out the last bit and it could be read in the 15th rising sclk edge. if goes low just after one the sclk falling edge has elapsed, will clock out the first leading zero as before and it may be read in the sclk rising edge. the next sclk falling edge will clock out the second leading zero and it could be read in the following rising edge. &6 t quiet 3-sta te t 5 t 8 b db0 t 7 sclk 1 s d at a 4 leading zero ? s ze ro zero zero z 3 -s tat e t 4 2 34 t 3 t convert t 2 db7 t 6 8bitsofdata 12 11 figure 16. AD7468 serial interface timing diagram
? 21 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 microprocessor interfacing the serial interface on the ad7466/ad7467/AD7468 allows the part to be directly connected to a range of many different microprocessors. this section explains how to interface the ad7466/ad7467/AD7468 with some of the more common microcontroller and dsp serial interface protocols. ad7466/67/68 to tms320c541 interface the serial interface on the tms320c541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the ad7466/67/68. the input allows easy interfacing between the tms320c541 and the ad7466/ 67/68 without any glue logic required. the serial port of the tms320c541 is set up to operate in burst mode (fsm=1 in the serial port control register, spc) with internal clkx (mcm=1 in the spc register) and interanl frame signal (txm = 1 in the spc register), so both pins are configured as outputs. for the ad7466 the word length should be set to 16 bits (fo=0 in the spc register). this dsp only allows frames with a word length of 16 or 8 bits. therefore, for the ad7467 and AD7468 where 14 and 12 bits are required, the fo bit would be set up to 16 bits also. in these cases, the user should keep in mind that, the last two and four bits for the ad7467 and AD7468 respectively, will be invalid data as the sdata line goes back into three-state on the 14th and 12th sclk falling edge. to summarise, the values in the spc register are: fo=0 fsm=1 mcm=1 txm=1 the connection diagram is shown in figure 17. it should be noted that for signal processing applications, it is imperative that the frame synchronisation signal from the tms320c541 will provide equidistant sampling. ad7466/67/68* sdata sclk &6 tms320c541* *additional pins omitted for clarity clkx clkr dr fsx fsr figure 17. interfacing to the tms320c541 ad7466/67/68 to adsp218x the adsp218x family of dsps are interfaced directly to the ad7466/67/68 without any glue logic required. the sport control register should be set up as follows: tfsw= rfsw= 1, alternate framing invrfs= invtfs= 1, active low frame signal dtype= 00, right justify data isclk= 1, internal serial clock tfsr= rfsr= 1, frame every word irfs= 0, it sets up rfs as an input itfs= 1, it sets up tfs as an output slen= 1111, 16 bits for the ad7466 slen= 1101, 14 bits for the ad7467 slen= 1011, 12 bits for the AD7468 the connection diagram is shown in figure 18. the adsp218x has the tfs and rfs of the sport tied together, with tfs set as an output and rfs set as an input. the dsp operates in alternate framing mode and the sport control register is set up as described. the frame synchronisation signal generated on the tfs is tied to and as with all signal processing applications equidistant sampling is necessary. however, in this ex- ample, the timer interrupt is used to control the sampling rate of the adc and, under certain conditions, equidistant sampling may not be achieved. the timer registers etc., are loaded with a value which will provide an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs and hence the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given, i.e. ax0= tx0, the state of the sclk is checked. the dsp will wait until the sclk has gone high, low and high before transmission will start. if the timer and sclk values are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, the data may be transmitted or it may wait until the next clock edge. for example, the adsp2111 has a master clock frequency of 16mhz. if the sclkdiv register is loaded with the value 3 then a sclk of 2mhz is obtained, and 8 master clock periods will elapse for every one sclk period. if the timer registers are loaded with the value 803, 100.5 sclks will occur between interrupts and subsequently between transmit instructions. this situation will result in non-equidistant sampling as the transmit instruction is occuring on a sclk edge. if the number of sclks between interrupts is a whole integer figure of n then equidistant sampling will be implemented by the dsp.
? 22 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 ad7466/67/68 to dsp563xx interface the connection diagram in figure 19 shows how the ad7466/67/68 can be connected to the ssi (synchronous serial interface) of the dsp563xx family of dsps from motorola. the ssi is operated in synchronous and normal mode (syn=1 and mod=0 in the control register b, crb) with internally generated 1-bit clock period frame sync for both tx and rx (bits fsl1=1 and fsl0=0 in the crb). set the word length in the control register a (cra) to 16 by setting bits wl2=0, wl1=1 and wl0=0 for the ad7466. the word length for the AD7468 can be set to 12 bits (wl2=0, wl1=0 and wl0=1). this dsp does not offer the option for a 14 bits word length, so the ad7467 word length will be set up to 16 bits like the ad7466. in this case, the user should bear in mind that the last two bits will be invalid data as the sdata goes back into three-state on the 14th sclk falling edge. the fsp bit in the crb register can be set to 1, that means that the frame goes low and a conversion starts. likewise, by means of the bits scd2, sckd and shfd in the crb register, it will be established that the pin sc2 (the frame sync signal) and sck in the serial port will be configured as outputs and the msb will be shifted first. to sum up, mod=0 syn=1 wl2, wl1, wl0 depend on the word length fsl1=1, fsl0=0 fsp=1, negative frame sync scd2=1 sckd=1 shfd=0 it should be noted that for signal processing applications, it is imperative that the frame synchronisation signal from the dsp563xx will provide equidistant sampling. figure 18. interfacing to the adsp218x ad7466/67/68* sclk &6 adsp218x* *additional pins omitted for clarity sclk dr rfs tfs sdata figure 19. interfacing to the dsp563xx ad7466/67/68* sdata sclk &6 dsp563xx* *additional pins omitted for clarity sck srd sc2
? 23 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 application hints grounding and layout the printed circuit board that houses the ad7466/67/68 should be designed such that the analog and digital sec- tions are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should be joined at only one place. if the ad7466/67/68 is in a system where multiple devices require an agnd to dgnd connection, the connection should still be made at one point only, a star ground point which should be established as close as possible to the ad7466/67/68. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7466/67/68 to avoid noise coupling. the power supply lines to the ad7466/67/68 should use as large a trace as possible to provide low im- pedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid cross- over of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also very important. all analog supplies should be decoupled with 10 f tantalum in parallel with 0.1 f capacitors to agnd. all digital supplies should have a 0.1 f disc ceramic capacitor to dgnd. to achieve the best performance from these decoupling components, the user should endeavour to keep the distance between the decoupling capacitor and the v dd and gnd pins to a minimum with short track lenghts connecting the respective pins. evaluating the ad7466/67 performance the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the pc via the eval- board controller. the eval-board controller can be used in conjunction with the ad7466/67cb evaluation board, as well as many other analog devices evaluation boards ending in the cb desig- nator, to demonstrate/evaluate the ac and dc performance of the ad7466/67. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7466/67. see the evaluation board technical note for more information.
? 24 ? rev. prf preliminary technical data ad7466/ad7467/AD7468 6-lead sot23 (rj-6) outline dimensions dimensions shown in millimeters 8 5 4 1 3.00 bsc pin 1 0.65 bsc 4.90 bsc 3.00 bsc seating plane 0.38 0.22 1.10 max 0.15 0.00 0.23 0.08 8 0 0.80 0.40 8-lead msop (rm-8) compliant to jedec standards mo-187aa compliant to jedec standards mo-178ab

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